Inter-process Communications for System-Level Design*
نویسندگان
چکیده
Working at system level is attracting increasing interest, as it supports the exploration of several alternatives, before the hardware/software partitioning takes place. New issues must be taken into account, such as validation and verification at all steps. Within the framework of a system-level design methodology that supports verification, communication protocols among processes play a key role. Protocols are presented that cover most relevant aspects useful in system-level, verifiable designs, together with the design for verifiability rules they entail both on the design methodology and on the use of VHDL as a description formalism.
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